1. Field of the Invention
Generally, the present disclosure relates to microstructures, such as advanced integrated circuits, and, more particularly, to conductive structures, such as copper-based metallization layers, comprising metal lines and vertical interconnects or vias.
2. Description of the Related Art
In the fabrication of modern microstructures, such as integrated circuits, there is a continuous drive to steadily reduce the feature sizes of microstructure elements, thereby enhancing the functionality of these structures. For instance, in modern integrated circuits, minimum feature sizes, such as the channel length of field effect transistors, have reached the deep sub-micron range, thereby increasing performance of these circuits in terms of speed and/or power consumption and/or diversity of functions. As the size of individual circuit elements is reduced with every new circuit generation, thereby improving, for example, the switching speed of the transistor elements, the available floor space for interconnect lines electrically connecting the individual circuit elements is also decreased. Consequently, the dimensions of these interconnect lines are also reduced to compensate for a reduced amount of available floor space and for an increased number of circuit elements provided per unit die area, as typically the number of interconnections required increases in an over-proportional manner relative the number of circuit elements. Thus, a plurality of stacked wiring layers, also referred to as metallization layers, are usually provided, wherein individual metal lines of one metallization layer are connected to individual metal lines of an overlying or underlying metallization layer by so-called vias. Despite the provision of a plurality of metallization layers, reduced dimensions of the interconnect lines are necessary to comply with the enormous complexity of, for instance, modern CPUs, memory chips, ASICs (application specific ICs) and the like.
Advanced integrated circuits, including transistor elements having a critical dimension of 0.05 μm and even less, may, therefore, typically be operated at significantly increased current densities of up to several kA per cm2 in the individual interconnect structures, despite the provision of a relatively large number of metallization layers, owing to the significant number of circuit elements per unit area. Consequently, well-established materials, such as aluminum, are being replaced by copper and copper alloys, a material with significantly lower electrical resistivity and improved resistance to electromigration, even at considerably higher current densities compared to aluminum. The introduction of copper into the fabrication of microstructures and integrated circuits comes along with a plurality of severe problems residing in copper's characteristic to readily diffuse in silicon dioxide and a plurality of low-k dielectric materials, which are typically used in combination with copper in order to reduce the parasitic capacitance within complex metallization layers. In order to provide the necessary adhesion and to avoid the undesired diffusion of copper atoms into sensitive device regions, it is, therefore, usually necessary to provide a barrier layer between the copper and the dielectric material in which the copper-based interconnect structures are embedded. Although silicon nitride is a dielectric material that effectively prevents the diffusion of copper atoms, selecting silicon nitride as an interlayer dielectric material is less than desirable, since silicon nitride exhibits a moderately high permittivity, thereby increasing the parasitic capacitance of neighboring copper lines, which may result in non-tolerable signal propagation delays. Hence, a thin conductive barrier layer that also imparts the required mechanical stability to the copper is usually formed so as to separate the bulk copper from the surrounding dielectric material, thereby reducing copper diffusion into the dielectric materials and also reducing the diffusion of unwanted species, such as oxygen, fluorine and the like, into the copper.
Furthermore, the conductive barrier layers may also provide highly stable interfaces with the copper, thereby reducing the probability of significant material transport at the interface, which is typically a critical region in view of increased diffusion paths that may facilitate current-induced material diffusion. Currently, tantalum, titanium, tungsten and their compounds, with nitrogen and silicon and the like, are preferred candidates for a conductive barrier layer, wherein the barrier layer may comprise two or more sub-layers of different composition so as to meet the requirements in terms of diffusion suppressing and adhesion properties.
Another characteristic of copper significantly distinguishing it from aluminum is the fact that copper may not be readily deposited in larger amounts by chemical and physical vapor deposition techniques, thereby requiring a process strategy that is commonly referred to as the damascene or inlaid technique. In the damascene process, first a dielectric layer is formed which is then patterned to include trenches and/or vias which are subsequently filled with copper, wherein, as previously noted, prior to filling in the copper, a conductive barrier layer is formed on sidewalls of the trenches and vias. The deposition of the bulk copper material into the trenches and vias is usually accomplished by wet chemical deposition processes, such as electroplating and electroless plating, thereby requiring the reliable filling of vias with an aspect ratio of 5 and more with a diameter of 0.3 μm or even less, in combination with trenches having a width ranging from 0.1 μm to several μm. Electrochemical deposition processes for copper are well established in the field of electronic circuit board fabrication. However, for the dimensions of the metal regions in semiconductor devices, the void-free filling of high aspect ratio vias is an extremely complex and challenging task, wherein the characteristics of the finally obtained copper-based interconnect structure significantly depend on process parameters, materials and geometry of the structure of interest. Since the basic geometry of interconnect structures is substantially determined by the design requirements and may, therefore, not be significantly altered for a given microstructure, it is of great importance to estimate and control the impact of materials, such as conductive and non-conductive barrier layers, of the copper microstructure and their mutual interaction on the characteristics of the interconnect structure so as to insure both high yield and the required product reliability.
In addition to achieving high production yield and superior reliability of the metallization system, it is also important to achieve production yield and reliability on the basis of a high overall throughput of the manufacturing process under consideration. For instance, the so-called dual damascene process is frequently used, in which a via opening and a corresponding trench are filled in a common deposition sequence, thereby providing superior process efficiency.
Upon further reducing the lateral dimensions of the metal features, the corresponding patterning process and a subsequent deposition of the conductive materials represent a very complex process sequence, for instance in terms of alignment accuracy, reliable void-free filling of the resulting openings in the dielectric material and the like. For example, in the inlaid technique, in which the via openings and the trenches for the metal lines are filled in a common deposition sequence, the via openings and the trenches have to be precisely adjusted, not only in view of superior electrical performance, but also in view of deposition-related aspects, since the filing in of conductive materials, such as barrier materials and the actual highly conductive fill metal, into a high aspect ratio via opening through a trench of lateral dimensions of several 100 nm and significantly less may per se represent a very challenging task. In frequently used approaches, the via opening may be formed first in the dielectric material of the metallization layer under consideration and subsequently the trench may be formed, wherein a trench mask may be provided prior to forming the via etch mask. Although this approach may result in a very efficient manufacturing strategy, problems may arise upon further shrinking the critical dimensions, as will be described with reference to FIGS. 1a-1i. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 comprising a substrate 101, which is to represent any appropriate material or material layers including circuit elements, such as transistors, capacitors, resistors and the like, as are typically required in sophisticated semiconductor devices. For convenience, any such circuit elements are not shown in FIG. 1a, wherein it should be appreciated, however, that these circuit elements, such as field effect transistors and the like, may be formed on the basis of critical dimensions of approximately 50 nm and less in sophisticated applications. Furthermore, the device 100 comprises a device layer or level 110, which may represent a metallization layer of the device 100 or which may represent any other device layer, such as a contact level and the like, or a semiconductor layer, in which circuit features are provided that need to be contacted via a metallization system of the device 100. For example, the device layer 110 may comprise a dielectric material 111, in which are embedded conductive regions 112, such as contact areas of transistors, metal lines, contact elements and the like. For example, the conductive regions 112 may comprise any appropriate conductive material, such as metal silicide, metals, highly-doped semiconductor materials and the like. Furthermore, the device 100 comprises a metallization layer 120, which may represent one of a plurality of metallization layers, since typically, in complex semiconductor devices, a plurality of stacked wiring levels may be required, as is also discussed above. The metallization layer 120 comprises a dielectric material 121, such as a low-k dielectric material, an ultra-low-k (ULK) material and the like, which are to be understood as dielectric materials having a dielectric constant of 3.0 or 2.7 and less. It should be appreciated that, typically, low-k dielectric materials, and in particular ULK materials, may have a significantly reduced mechanical stability due to a reduced material density, which may be considered appropriate for obtaining the low values of the dielectric constant. Similarly, such materials may be sensitive with respect to the exposure to reactive process atmospheres, such as plasma-assisted etch processes and the like. Consequently, frequently, a dielectric cap material 123, for instance in the form of silicon dioxide and the like, may be provided so as to enhance the overall stability of the low-k dielectric material 121. Furthermore, an etch stop material 122, such as silicon carbide based materials including nitrogen and the like, or combinations of various materials, are typically used, which represent a compromise between dielectric behavior and etch resistivity.
Furthermore, in the manufacturing stage shown, a hard mask material 102 is formed above the dielectric materials of the metallization layer 120, which is used during the patterning of the dielectric materials 123, 121 and 122 upon providing appropriate trenches and via openings for the metallization layer 120. The hard mask material 102 may be provided in the form of a plurality of materials, such as titanium nitride, titanium, tantalum nitride, aluminum and the like, which may provide high etch resistivity at a reduced layer thickness. Furthermore, a resist mask 103 is formed above the hard mask material 102 and comprises openings 103A, which substantially determine the lateral size and position of metal lines to be formed in the metallization layer 120.
Typically, the semiconductor device 100 may be formed on the basis of the following process techniques. After providing any circuit elements in and above the substrate 101 in accordance with the overall device requirements, the device layer 110 is formed in accordance with any desired process strategy. It may be assumed, in this example, that the layer 110 represents a metallization layer and the conductive regions 112 represent metal lines of the layer 110. In this case, similar process techniques may be applied as will be explained for the metallization layer 120. Hence, after completing the layer 110, the etch stop material 122 is deposited, for instance, by plasma-enhanced chemical vapor deposition (CVD) on the basis of well-established deposition recipes, thereby appropriately providing material composition and layer thickness of the etch stop material 122. It should be appreciated that the layer 122 may comprise two or more sub-layers, depending on the overall process requirements. Thereafter, the dielectric material 121 is formed by any appropriate deposition technique, such as CVD, spin-on techniques and the like, depending on the characteristics of the material 121. For example, a plurality of silicon dioxide based materials having a reduced material density are well established in the art and may be used for the material 121. Frequently, additional treatments may be applied so as to further reduce the overall dielectric constant, for instance by reducing the material density and the like, thereby, however, also typically reducing the overall stability of the material 121. Next, the material layer 123 may be formed so as to impart superior stability to the sensitive dielectric material 121. The hard mask material 102 may be formed on the basis of any appropriate deposition technique, such as physical vapor deposition (PVD), CVD and the like. Thereafter, any further materials, if required, may be provided so as to finally form the resist mask 103 on the basis of sophisticated lithography techniques. It should be appreciated that the opening 103A may have a lateral critical dimension of several hundred nanometers and significantly less, depending on the metallization level and the complexity of the semiconductor device 100. For example, the opening 103A may have a width of 100 nm and less. On the basis of the resist material 103, the hard mask material 102 may be patterned by using plasma-assisted etch recipes, wherein the material layer 123 may act as an efficient etch stop material in order to avoid undue interaction of the reactive etch ambient with the sensitive dielectric material 121.
FIG. 1b schematically illustrates the device 100 after the removal of the resist mask 103 (FIG. 1a) and with corresponding mask openings 102A, which may substantially correspond in size and position to the openings 103A as shown in FIG. 1a. Consequently, the mask openings 102A may thus define the size and position of trenches to be formed in the dielectric materials 123 and 121.
FIG. 1c schematically illustrates the device 100 with a further etch mask 104 formed above the hard mask 102 in order to define the lateral size and position of via openings to be formed so as to connect to the conductive regions 112. As is illustrated, the openings 104A may thus expose a portion of the mask openings 102A, wherein, depending on the alignment accuracy upon forming the mask 104, a certain degree of misalignment may occur so that the opening 104A and the mask opening 102A may not be perfectly aligned to each other, although these openings may have substantially the same lateral dimensions in the horizontal direction of FIG. 1c. That is, typically, a via opening may have to be provided with substantially the same lateral dimensions as a trench in order to avoid undue local extensions of the metal lines, which could otherwise result in increased leakage currents between adjacent metal lines that are to be formed on the basis of the mask openings 102A in a later manufacturing stage.
FIG. 1d schematically illustrates a top view of the device 100 according to the manufacturing stage as shown in FIG. 1c. As illustrated, the openings 104A may be slightly misaligned with respect to the mask openings 102A, thereby exposing the material 123 and a portion of the material 102 within the openings 104A. Consequently, a distance 102D may be reduced compared to a desired target distance upon actually forming the metal lines and vias on the basis of the mask arrangement as shown in FIG. 1d, so that corresponding increased process tolerance may have to be taken into consideration upon designing the semiconductor device 100.
FIG. 1e schematically illustrates the device 100 in a cross-sectional view when exposed to an etch process 105, in which an appropriate plasma-assisted etch recipe is applied so as to etch through the material 123 and finally through the material 121 on the basis of the masks 102 and 104. In the example shown, the etch process 105 is performed on the basis of an etch chemistry that is substantially not selective with respect to the mask material 102 so as obtain the desired target width of a via opening 121V, which would otherwise be reduced by a difference D as shown in FIG. 1e due to the misalignment between the openings 104A and 102A, as discussed above. In this case, however, the distance between two neighboring metal lines will be reduced, as previously explained with reference to FIG. 1d. 
FIG. 1f schematically illustrates the device 100 according to a further strategy, in which the probability of any misalignments may be reduced by providing the via etch mask 104 with openings 104B having an increased lateral dimension along the width direction, which is to be understood as the horizontal direction in FIG. 1f. That is, the etch mask 104 is provided on the basis of an increased dimension, which is selected such that any process variations during the lithography process are taken into consideration and are accommodated in the lateral dimension in the opening 104B. Consequently, in this case, a maximum allow-able process variation during the patterning of the etch mask 104 may still result in a complete exposure of the mask opening 102A.
FIG. 1g schematically illustrates a top view of the device 100 according to this strategy, wherein the openings 104B may have appropriate dimensions, or may have a lateral extension compared to the openings 104A as shown in FIG. 1d, that ensure the alignment of the openings 104B and 102A.
The mask 104 is typically provided in the form of an organic material, such as a resist material or as a polymer material, possibly including two or more individual material layers so as to provide a superior surface topography, and also providing anti-reflective coating (ARC) capabilities, if required. For example, resist materials or any other polymer materials may be efficiently applied by spin-on techniques, followed by appropriate treatments and a subsequent exposure on the basis of appropriate photomasks, which may have appropriate mask features for providing the openings 104A or 104B, depending on the selected process strategy.
FIG. 1h schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage, when using the self-aligned mask 104 including the mask openings 104B in combination with the etch process 105, which is now to be performed on the basis of an etch chemistry that exhibits a high selectivity with respect to the mask 102. Consequently, in the horizontal direction, the corresponding via openings 121V are delineated by the mask opening 102A and are thus self-aligned to corresponding trenches, which are to be formed in a later manufacturing stage on the basis of the hard mask layer 102. After the etch process 105, which may be appropriately controlled on the basis of the etch stop layer 122, the mask 104 is removed, for instance, by oxygen plasma, wet chemical etch recipes and the like, followed by a further anisotropic etch process, which may, for instance, be performed on the basis of a similar etch chemistry as the process 105, so as to form trenches in the dielectric material 121.
FIG. 1i schematically illustrates the device 100 in a further advanced manufacturing stage. As illustrated, a conductive barrier material 124 is formed within the via opening 121V and thus also in a trench formed in the dielectric material 121 in an upper portion of the material 121 extending in a direction perpendicular to the drawing plane of FIG. 1i. Furthermore, a conductive fill material 125, such as a copper material, is formed in the via opening 121V, thereby providing a desired high conductivity. In the example shown, the hard mask 102 may still be present and may be removed together with any excess material of the layers 124, 125, for instance on the basis of a chemical mechanical polishing (CMP) process. In other cases, the material 102 may be removed prior to filing in the materials 124, 125, in order to reduce the resulting aspect ratio, in particular for the via opening 121V. The deposition of the material 124 and also of the material 125 may thus require the deposition into a high aspect ratio so that an increased layer thickness for the barrier layer 124 may be required so as to reliably cover any critical areas within the via opening 121V. On the other hand, the via openings 121V may be reduced in width at the upper edges thereof during the deposition of the material 124, when reliably covering, in particular, the sidewall areas at the bottom of the via 121V, so that the subsequent deposition of the actual fill material 125 may also be inferior, at least within the vias 121V. Therefore, in some process strategies, the hard mask 102 is removed prior to depositing the materials 124 and 125, possibly in combination with a certain degree of corner rounding, which, however, may result in undue exposure of the sensitive material 121 to reactive process atmospheres, which may thus result in undue damage of the low-k material.
Consequently, although the self-aligned approach for forming the via openings 121V may result in a precise alignment of trenches and via openings, extremely sophisticated process conditions may have to be dealt with upon filling in the conductive materials.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.